The present invention relates to a divide by n circuit, where n is an interger, for use in generating a second clock signal of frequency f/n from a first clock signal of frequency f.
In response to pressure for incorporating more and more circuitry onto a circuit board there has developed pressure to save board space by reducing the number of separate packages wherever possible. A reduction in the number of separate packages makes it attractive to place as much circuitry as possible onto a given semiconductor chip or within a given package. One way of meeting this challenge is to reduce the number of separate oscillators required and to generate one or more clock signals from a single oscillator circuit. Division of a master oscillator clock frequency by a factor of 2,4,8 etc. is relatively straight forward through the use of standard divide by 2 circuits and produces an output duty cycle of about 50%. However, if a division by an odd factor is required, then generally a poor duty cycle results. Typically, for example, a divide by 3 circuit is made by simple logic that pulls the output high (or low) for one cycle and then low (or high) for 2 cycles producing an output clock with only a 33% duty cycle. Other methods for achieving a higher duty cycle exist using phase lock loops or other linear feedback circuits that obtain acceptable results with linear processing but not with digital processing.
Accordingly, an object of the present inventions is to provide an improved divide by n circuit where n is an odd whole number.